1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor apparatus with a plurality of individual stacked chips.
2. Related Art
A semiconductor apparatus is designed to operate at a high speed with a data storage region of a large capacity.
To this end, a technique to stack individual chips in a wafer level and packaging them to manufacture individual products is developed.
Generally, the respective stacked individual chips are assigned addresses and data are stored in the chips using the assigned addresses.
When addresses are assigned to the respective stacked individual chips, the assigned addresses are designated by sequentially increasing or decreasing the values of codes consisting of a plurality of bits.
Such technologies to assign sequentially increasing or decreasing code values to stacked individual chips as addresses are used based on the assumption that any stacked individual chips have not failed.
However, if one of the stacked individual chips has failed, all the stacked individual chips cannot be used. For example, in a semiconductor apparatus having eight layers, failure of only one individual chip would render the remaining seven non-failed chips unusable, which reduces efficiency and productivity.